CACTI — Cache Area, Timing & Power Modeling

Contents

Architecture

CACTI models a cache as a hierarchy of components. The top-level solver (Ucache) partitions the array and delegates to UCA/Nuca, which compose banks, mats, subarrays, decoders, and H-tree routing networks.

classDiagram
    class Component {
        +Area area
        +powerDef power
        +double delay
        +double cycle_time
    }
    class UCA {
        +Bank bank
        +Htree2* htree_in_add
        +Htree2* htree_in_data
        +Htree2* htree_out_data
        +compute_delays()
        +compute_power_energy()
    }
    class Bank {
        +Mat mat
        +Htree2* htree_in_add
        +int num_mats_hor_dir
        +compute_delays()
    }
    class Mat {
        +Subarray subarray
        +Decoder* row_dec
        +Predec* r_predec
        +Wire* subarray_out_wire
        +compute_delays()
        +compute_bitline_delay()
        +compute_sa_delay()
    }
    class Subarray {
        +uint num_rows
        +uint num_cols
        +double C_wl, R_wl, C_bl
        +get_total_cell_area()
    }
    class Wire {
        +Wire_type wt
        +double repeater_size
        +double repeater_spacing
        +calculate_wire_stats()
        +delay_optimal_wire()
        +wire_cap()
        +wire_res()
    }
    class Decoder {
        +int num_in_signals
        +int num_gates
        +compute_widths()
        +compute_delays()
    }
    class Htree2 {
        +Htree_type tree_type
        +int add_bits, data_in_bits
        +in_htree()
        +out_htree()
    }
    class Crossbar {
        +double n_inp, n_out
        +double flit_size
        +compute_power()
    }
    class MCPAT_Router {
        +Component arbiter
        +Component crossbar
        +Component buffer
        +calc_router_parameters()
    }
    Component <|-- UCA
    Component <|-- Bank
    Component <|-- Mat
    Component <|-- Subarray
    Component <|-- Wire
    Component <|-- Decoder
    Component <|-- Htree2
    Component <|-- Crossbar
    Component <|-- MCPAT_Router
    UCA *-- Bank
    UCA *-- Htree2
    Bank *-- Mat
    Bank *-- Htree2
    Mat *-- Subarray
    Mat *-- Decoder
    Mat *-- Wire
    MCPAT_Router *-- Crossbar

Data Flow — Cache Parameter Search

When AccelWattch needs power/area/timing for a cache structure, it calls cacti_interface() which triggers an exhaustive multi-threaded search over the partition space.

sequenceDiagram
    participant AW as AccelWattch (ArrayST)
    participant CI as cacti_interface()
    participant UC as Ucache::solve()
    participant CT as calculate_time()
    participant MT as Mat
    participant SA as Subarray
    participant WR as Wire
    participant UCA as UCA (assemble)

    AW->>CI: cacti_interface(InputParameter)
    CI->>CI: init_tech_params(F_sz_nm)
    CI->>UC: solve(&fin_res)
    UC->>UC: spawn N threads
    loop For each (Ndwl, Ndbl, Nspd, Ndcm, Ndsam) partition
        UC->>CT: calculate_time(is_tag, partition_params)
        CT->>SA: Subarray(rows, cols, cell)
        SA-->>CT: cell area, C_wl, C_bl
        CT->>MT: Mat(subarray, decoders, wire)
        MT->>MT: compute_bitline_delay()
        MT->>MT: compute_sa_delay()
        MT->>WR: Wire(type, length)
        WR-->>MT: wire delay, wire power
        MT-->>CT: mat delay, mat power, mat area
        CT-->>UC: mem_array* result
    end
    UC->>UC: filter_tag_arr(min_values)
    UC->>UC: filter_data_arr(min_values)
    UC->>UCA: UCA(tag_arr, data_arr)
    UCA->>UCA: combine via Htree2 routing
    UCA-->>UC: uca_org_t (access_time, power, area)
    UC-->>CI: fin_res
    CI-->>AW: uca_org_t result

Key Classes

Data Structures

Interactions with AccelWattch

CACTI is the analytical engine underneath AccelWattch. Every on-chip SRAM/CAM structure in the GPU power model is dimensioned by CACTI.

Configuration Knobs

CACTI accepts cache geometry via InputParameter (programmatic API) or cache.cfg (file-based). Key parameters:

Directory Map

cacti/
├── cacti_interface.h/.cc      ← Public API: InputParameter, powerDef, uca_org_t, cacti_interface()
├── Ucache.h/.cc               ← Unified cache solver: solve(), filter_tag_arr(), filter_data_arr()
├── uca.h/.cc                  ← Unified Cache Architecture: tag+data banks + H-tree assembly
├── bank.h/.cc                 ← Bank-level model: mat aggregation + H-tree routing
├── mat.h/.cc                  ← Mat (matrix) model: bitline/wordline delay, sense-amp, mux (~82 KB)
├── subarray.h/.cc             ← Subarray cell array: physical dimensions, parasitic R/C
├── decoder.h/.cc              ← Row/column decoders + predecoders (Predec, PredecBlk, Driver)
├── wire.h/.cc                 ← Wire delay/power: repeater insertion, low-swing, 5 wire types
├── htree2.h/.cc               ← H-tree routing: address, data-in, data-out distribution
├── area.h/.cc                 ← Area accounting: width × height geometry container
├── component.h/.cc            ← Base Component class: area, power, delay, gate-level helpers
├── parameter.h/.cc            ← DynamicParameter: runtime partition factors from InputParameter
├── router.h/.cc               ← MCPAT_Router: 2D mesh router (crossbar + VC buffers + arbiter)
├── crossbar.h/.cc             ← Crossbar switch: N×M tri-state buffer matrix
├── arbiter.h/.cc              ← Arbiter logic: VC arbitration, priority encoding, grant signals
├── nuca.h/.cc                 ← Non-Uniform Cache Architecture: mesh routing + contention
├── highradix.h/.cc            ← High-radix router: sub-switch decomposition, row/col buffers
├── basic_circuit.h/.cc        ← Transistor primitives: leakage, capacitance, logical effort
├── technology.cc              ← ~130 KB ITRS technology database (22–180 nm nodes)
├── io.h/.cc                   ← I/O and reporting: config parsing, result formatting (~84 KB)
├── const.h                    ← Array size limits, Vth constants, gate type enums
├── main.cc                    ← Standalone CACTI entry point (command-line tool)
├── cache.cfg                  ← Default cache configuration file
├── cacti.mk                   ← Makefile fragment for CACTI library build
├── cacti.i                    ← SWIG interface (Python/Perl bindings)
├── README                     ← Original HP Labs CACTI readme
├── batch_tests/               ← Batch test scripts
├── contention.dat             ← Contention lookup table for NUCA
└── out_batch_test_result.csv  ← Sample batch test output

Deep-Dive Highlights

Core mechanisms from the CACTI sub-module have been extracted into dedicated focus areas. Each covers one subsystem with diagrams, code walks, and configuration details.

Deep-Dive Pages

Code Examples

Example 1: Calling CACTI from AccelWattch

// array.cc — ArrayST calls CACTI to size an SRAM array
ArrayST::ArrayST(const InputParameter *ip, string name, ...) {
    l_ip = *ip;  // copy cache geometry into local InputParameter
    l_ip.error_checking();

    // Call CACTI solver — returns timing, area, power
    local_result = cacti_interface(&l_ip);

    // Extract results into Component base class fields
    area.set_area(local_result.area * 1e6);  // mm² → µm²
    power = local_result.power;
    delay = local_result.access_time;
    cycle_time = local_result.cycle_time;
}

Example 2: Multi-threaded Partition Search (solve)

// Ucache.cc — exhaustive search over partition space
void solve(uca_org_t *fin_res) {
    init_tech_params(g_ip->F_sz_um, false);

    list<mem_array *> tag_arr(0), data_arr(0);

    // Spawn N threads, each searching a slice of the
    // (Ndwl × Ndbl × Nspd × Ndcm × Ndsam) partition space
    calc_time_mt_wrapper_struct *calc_array =
        new calc_time_mt_wrapper_struct[nthreads];
    pthread_t threads[nthreads];

    for (uint32_t t = 0; t < nthreads; t++) {
        calc_array[t].tid      = t;
        calc_array[t].pure_ram = pure_ram;
        pthread_create(&threads[t], NULL,
                       calc_time_mt_wrapper, &calc_array[t]);
    }
    for (uint32_t t = 0; t < nthreads; t++)
        pthread_join(threads[t], NULL);

    // Merge results and filter dominated solutions
    filter_tag_arr(&data_min, tag_arr);
    filter_data_arr(data_arr);

    // Combine best tag + data arrays via UCA/Htree
    // → fin_res contains optimal (access_time, power, area)
}

Example 3: Wire Delay with Repeater Optimization

// wire.cc — optimal repeater insertion for global wires
void Wire::delay_optimal_wire() {
    double len = wire_length;
    double r = wire_res(len);   // total wire resistance
    double c = wire_cap(len);   // total wire capacitance

    // Elmore delay without repeaters: τ = 0.5·R·C
    // With repeaters: insert every spacing_opt with size_opt
    repeater_spacing = sqrt(
        2 * deviceType->R_nch_on * deviceType->C_g_ideal /
        (wire_res(1) * wire_cap(1)));
    repeater_size =
        sqrt(wire_res(1) * wire_cap(1) /
             (deviceType->R_nch_on * deviceType->C_g_ideal));

    // Calculate buffered wire delay
    delay = repeater_spacing * wire_res(repeater_spacing) *
            (wire_cap(repeater_spacing) +
             deviceType->C_g_ideal * repeater_size);
    power.readOp.dynamic = 0.5 * repeater_size *
        deviceType->C_g_ideal * g_tp.peri_global.Vdd *
        g_tp.peri_global.Vdd * (len / repeater_spacing);
}