dev — Device Models

flowchart LR
  subgraph BaseClasses["Base Device Classes"]
    CO["ClockedObject"]
    PIO["PioDevice\n<i>PioPort for MMIO</i>"]
    BPIO["BasicPioDevice\n<i>fixed addr + size</i>"]
    DMA["DmaDevice\n<i>+ DmaPort for DMA</i>"]
  end

  subgraph PCIStack["PCI Stack"]
    PCID["PciDevice\n<i>config space, BARs</i>"]
    PCIE["PciEndpoint\n<i>Type 0 header</i>"]
    PCIB["PciType1Device\n<i>Bridge / Type 1</i>"]
    HOST["PciHost\n<i>root complex</i>"]
    BUS["PciBus\n<i>non-coherent xbar</i>"]
  end

  subgraph NetDevices["Network"]
    ELINK["EtherLink\n<i>point-to-point</i>"]
    EBUS["EtherBus\n<i>shared medium</i>"]
    ESWITCH["EtherSwitch"]
    NIC["NsGigE / IGbE / Sinic"]
  end

  subgraph StorageDevices["Storage"]
    IDEC["IdeController"]
    IDED["IdeDisk"]
    DIMG["DiskImage"]
  end

  subgraph VirtIODevices["VirtIO"]
    VDB["VirtIODeviceBase"]
    VQ["VirtQueue"]
    VBK["VirtIOBlock"]
    VCN["VirtIOConsole"]
  end

  subgraph Platform["Platform & Interrupts"]
    PLAT["Platform\n<i>interrupt routing</i>"]
  end

  CO --> PIO
  PIO --> BPIO
  PIO --> DMA
  DMA --> PCID
  PCID --> PCIE
  PCID --> PCIB
  HOST --> BUS
  PCIE --> NIC
  BPIO --> IDEC
  PLAT --> HOST
  DMA -.->|"DmaPort"| MEMBUS["Memory Bus"]
  PIO -.->|"PioPort"| MEMBUS
  NIC --> ELINK
  ELINK --> EBUS
  IDEC --> IDED
  IDED --> DIMG
  VDB --> VQ
  VDB --> VBK
  VDB --> VCN

sequenceDiagram
    participant CPU as CPU Core
    participant BUS as Memory Bus
    participant NIC as NIC Device
    participant DMAPORT as DMA Port
    participant RAM as System Memory

    Note over CPU,RAM: PIO Read — CPU reads a device register
    CPU->>BUS: ReadReq (device MMIO addr)
    BUS->>NIC: PioPort.recvAtomic(pkt)
    NIC->>NIC: read(pkt) — decode register
    NIC-->>BUS: Response with data
    BUS-->>CPU: Data returned

    Note over CPU,RAM: DMA Write — Device writes to host memory
    NIC->>DMAPORT: dmaWrite(addr, size, data)
    DMAPORT->>DMAPORT: ChunkGenerator splits request
    DMAPORT->>BUS: WriteReq (chunk 1)
    BUS->>RAM: Store data
    RAM-->>BUS: WriteResp
    BUS-->>DMAPORT: Response
    DMAPORT->>BUS: WriteReq (chunk 2)
    BUS->>RAM: Store data
    RAM-->>DMAPORT: Response
    DMAPORT->>NIC: completionEvent fired

    Note over CPU,RAM: Interrupt — Device signals CPU
    NIC->>NIC: intrPost()
    NIC-->>CPU: Interrupt delivered via Platform

flowchart TD
  subgraph dev["dev Module"]
    PIO["PioDevice"]
    DMA["DmaDevice"]
    PLAT["Platform"]
  end
  subgraph mem["mem Module"]
    MBUS["MemBus / CoherentXBar"]
    PORT["Port (Request/Response)"]
    DRAM["DRAM Controller"]
  end
  subgraph cpu["cpu Module"]
    CPUCORE["CPU Core"]
    INT["Interrupt Handler"]
  end
  subgraph sim["sim Module"]
    SYS["System"]
    EVTQ["EventQueue"]
  end

  PIO -->|"PioPort"| PORT
  DMA -->|"DmaPort"| PORT
  PORT --> MBUS
  MBUS --> DRAM
  PLAT -->|"postInt / clearInt"| INT
  INT --> CPUCORE
  SYS -->|"owns"| PIO
  SYS -->|"owns"| DMA
  EVTQ -->|"schedules"| DMA