x86 — x86-64 ISA Implementation

Architecture Overview

The x86 ISA is one of gem5's most complex architecture implementations due to the CISC nature of x86-64. Key challenges include variable-length instruction encoding (1-15 bytes), the microcode decomposition of complex instructions, legacy segmentation support, and the full Local APIC interrupt controller model.

graph TB
    subgraph "Decoder Pipeline"
      Fetch["Byte Stream"]
      Prefix["Prefix Parsing\n(REX, VEX, EVEX)"]
      Opcode["Opcode Decode"]
      ModRM["ModR/M + SIB"]
      Micro["Microcode ROM\n(complex insts)"]
      SI["StaticInst"]
    end

    subgraph "ISA State"
      Regs["Register File\n(16 GPRs, XMM, flags)"]
      Segs["Segment Registers\n(CS, DS, SS, ES, FS, GS)"]
      CPUID_["CPUID Database"]
      MSRs["Model-Specific Regs"]
    end

    subgraph "System"
      APIC["Local APIC\n(interrupt controller)"]
      MMU["x86 MMU\n(4-level page tables)"]
      TLB["x86 TLB"]
    end

    Fetch --> Prefix --> Opcode --> ModRM --> SI
    Opcode -->|"complex"| Micro --> SI
    SI --> Regs
    APIC --> Regs
    MMU --> TLB
    

Instruction Decoder

The x86 decoder is a state-machine-based parser that handles the full complexity of x86 instruction encoding. It processes bytes sequentially through states: prefix parsing, opcode identification, ModR/M/SIB decoding, and displacement/immediate extraction.

namespace X86ISA {

class Decoder : public InstDecoder
{
  public:
    // Decoder states
    enum State {
        ResetState,
        PrefixState,
        TwoByteOpcodeState,
        ThreeByte0F38State,
        ThreeByte0F3AState,
        VexTwoByteState,
        VexThreeByteState,
        OneByteOpcodeState,
        ModRMState,
        SIBState,
        DisplacementState,
        ImmediateState,
        // ... additional states
    };

    void moreBytes(const PCStateBase &pc, Addr fetchPC) override;
    bool instReady() const override;
    StaticInstPtr decode(PCStateBase &nextPC) override;
    void reset() override;

  private:
    State state;
    ExtMachInst emi;        // Extended machine instruction
    uint8_t prefixes;        // Accumulated prefix bytes
    uint8_t rexPrefix;       // REX prefix for 64-bit mode
    int immediateSize;
    int displacementSize;

    // Microcode ROM for complex instructions
    StaticInstPtr decodeInst(ExtMachInst mach_inst);
};

Microcode Engine

Complex x86 instructions (e.g., REP MOVSB, CPUID, XSAVE) are decomposed into sequences of micro-operations. The microcode ROM maps each macroop to a sequence of microops that the CPU pipeline processes individually.

// A macroop decomposes into microops
class MacroopBase : public StaticInst
{
  protected:
    std::vector<StaticInstPtr> microops;
    uint32_t numMicroops;

  public:
    StaticInstPtr fetchMicroop(MicroPC upc) const override {
        return microops[upc];
    }
    bool isMacroop() const override { return true; }
    bool isMicroop() const override { return false; }
};

// Individual microop
class MicroopBase : public X86ISA::X86StaticInst
{
  public:
    bool isMicroop() const override { return true; }
    bool isLastMicroop() const override;
    bool isFirstMicroop() const override;
};

Register File

Fault Handling

x86 defines a complex fault hierarchy mapping to processor exceptions. Each fault carries a vector number and optional error code pushed onto the stack during exception delivery.

namespace X86ISA {

class X86Fault : public FaultBase
{
  protected:
    const char *faultName;
    uint8_t vector;       // IDT vector number
    bool errorCode;       // Whether error code is pushed

  public:
    void invoke(ThreadContext *tc, const StaticInstPtr &inst) override;
};

// Specific faults
class DivideError : public X86Fault { /* vector 0 */ };
class DebugException : public X86Fault { /* vector 1 */ };
class Breakpoint : public X86Fault { /* vector 3 */ };
class InvalidOpcode : public X86Fault { /* vector 6 */ };
class PageFault : public X86Fault {
    Addr addr;
    uint32_t errorCode;  // P, W/R, U/S, RSVD, I/D bits
};
class GeneralProtection : public X86Fault { /* vector 13 */ };

} // namespace X86ISA

Local APIC

The Local APIC (Advanced Programmable Interrupt Controller) model handles interrupt delivery, IPI (Inter-Processor Interrupt) routing, timer functionality, and interrupt prioritization.

class Interrupts : public BaseInterrupts
{
  public:
    // APIC registers
    uint32_t regs[NUM_APIC_REGS];

    // Interrupt request/service registers (256 bits each)
    ApicRegister IRR;  // Interrupt Request Register
    ApicRegister ISR;  // In-Service Register

    // Timer
    uint32_t initialCount;
    uint32_t currentCount;
    Tick timerPeriod;

    // Check for pending interrupts
    bool checkInterrupts() const override;
    Fault getInterrupt() override;
    void updateIntrInfo() override;

    // IPI interface
    void sendIPI(uint8_t destId, uint8_t vector, uint8_t deliveryMode);

    // MMIO interface for APIC register access
    Tick read(PacketPtr pkt) override;
    Tick write(PacketPtr pkt) override;
};

CPUID Emulation

gem5 emulates CPUID responses to correctly identify the simulated processor's capabilities to guest software. The CPUID database returns appropriate feature flags, Cache Hierarchy | gem5 Wiki" href="../../mem_doc/cache/index.html">cache topology, and vendor information.

// CPUID leaf 0: Vendor string
// Returns "GenuineIntel" or "AuthenticAMD" based on config

// CPUID leaf 1: Feature flags
// Reports supported extensions: SSE, SSE2, SSE3, SSSE3,
// SSE4.1, SSE4.2, POPCNT, CLFLUSH, etc.

// CPUID leaf 4: Cache topology
// Reports L1I, L1D, L2, L3 cache parameters

// CPUID leaf 0x80000000+: Extended features
// Reports long mode support, NX bit, etc.

Key Components Reference

Glossary