minor

Pipeline Architecture

The MinorCPU pipeline is contained in the Pipeline class (minor/pipeline.hh), which owns the four stages and the MinorBuffer FIFO queues between them. The MinorCPU class (minor/cpu.hh) inherits from BaseCPU and owns the Pipeline instance, the activity recorder, and per-thread state.

flowchart LR
    subgraph Pipeline["minor::Pipeline"]
        F1["Fetch1\nfetch1.hh"]
        F2["Fetch2\nfetch2.hh"]
        DEC["Decode\ndecode.hh"]
        EXE["Execute\nexecute.hh"]
    end
    subgraph Support["Support Structures"]
        SB["Scoreboard\nscoreboard.hh"]
        LSQ["LSQ\nlsq.hh"]
        FU["FuncUnit\nfunc_unit.hh"]
        DI["MinorDynInst\ndyn_inst.hh"]
    end
    subgraph Memory["Memory System"]
        IC["ICache Port"]
        DC["DCache Port"]
    end

    F1 -->|"LineBuffer"| F2
    F2 -->|"InstBundle"| DEC
    DEC -->|"InstBundle"| EXE
    F1 -->|"fetch request"| IC
    EXE -->|"load/store"| LSQ
    LSQ -->|"memory request"| DC
    EXE --- SB
    EXE --- FU
    F2 --- DI

Pipeline Stages in Detail

Fetch1 — Line Fetch

Fetch1 (minor/fetch1.hh) is responsible for fetching raw cache lines from the instruction cache. It generates fetch requests based on the current PC, handles ITLB misses by initiating page walks, and manages the fetch buffer. When the branch predictor redirects the PC, Fetch1 discards in-flight fetch requests and starts fetching from the new target.

Fetch2 — Line Decomposition

Fetch2 (minor/fetch2.hh) takes the raw cache line bytes from Fetch1 and uses the ISA decoder to decompose them into individual MinorDynInst objects. It handles variable-length instruction sets (like x86) by tracking the decode position within the line. Branch prediction also happens here — Fetch2 consults the branch predictor for each control-flow instruction and updates the fetch PC accordingly.

Decode — Micro-op Expansion

Decode (minor/decode.hh) expands macro-ops into micro-ops for ISAs that require it (e.g., x86 complex instructions). For RISC ISAs like ARM or RISC-V where most instructions are already single micro-ops, this stage is largely a pass-through. The decode stage also classifies instructions by type for the Execute stage.

Execute — Scoreboard & Functional Units

Execute (minor/execute.hh) is the most complex stage. It performs hazard checking using the Scoreboard, dispatches instructions to FuncUnit pipelines, handles memory operations through the LSQ, and manages instruction completion. The Execute stage stalls the pipeline when a data hazard is detected (read-after-write on a register not yet produced) or when a structural hazard occurs (no available functional unit).

Key Classes

Data Flow Diagram

sequenceDiagram
    participant IC as ICache
    participant F1 as Fetch1
    participant F2 as Fetch2
    participant DEC as Decode
    participant EXE as Execute
    participant SB as Scoreboard
    participant DC as DCache

    F1->>IC: sendTimingReq(PC)
    IC-->>F1: cache line response
    F1->>F2: ForwardLineData (raw bytes)
    F2->>F2: ISA decode: bytes → instructions
    F2->>F2: branch predict each control inst
    F2->>DEC: ForwardInstData (inst bundle)
    DEC->>DEC: macro-op → micro-op expansion
    DEC->>EXE: ForwardInstData (micro-ops)
    EXE->>SB: check source register readiness
    alt RAW hazard detected
        SB-->>EXE: stall (source not ready)
        Note over EXE: pipeline bubbles until ready
    else all sources ready
        EXE->>EXE: dispatch to FuncUnit
        EXE->>EXE: execute (1+ cycles)
        alt memory instruction
            EXE->>DC: sendTimingReq(addr)
            DC-->>EXE: data response
        end
        EXE->>SB: mark dest register ready
        EXE->>EXE: commit instruction
    end

Pipeline Hazards

MinorCPU handles three types of hazards through stalling and forwarding:

Key difference from O3: MinorCPU does not rename registers or reorder instructions. WAR and WAW hazards cannot occur because instructions execute strictly in program order. Only RAW, structural, and control hazards need handling.

Cross-Module Interactions

Directory Map

minor/
├── cpu.hh / cpu.cc               ← MinorCPU: top-level CPU class
├── pipeline.hh / pipeline.cc     ← Pipeline: stage container, evaluate() driver
├── fetch1.hh / fetch1.cc         ← Fetch1: cache line fetch, ITLB
├── fetch2.hh / fetch2.cc         ← Fetch2: instruction decode, branch predict
├── decode.hh / decode.cc         ← Decode: macro → micro-op expansion
├── execute.hh / execute.cc       ← Execute: hazard check, dispatch, commit
├── scoreboard.hh / scoreboard.cc ← Scoreboard: register readiness tracking
├── lsq.hh / lsq.cc              ← LSQ: memory operation management
├── func_unit.hh / func_unit.cc   ← FuncUnit: configurable execution units
├── dyn_inst.hh / dyn_inst.cc     ← MinorDynInst: dynamic instruction
├── buffers.hh                    ← MinorBuffer: inter-stage FIFO template
├── pipe_data.hh / pipe_data.cc   ← ForwardLineData, ForwardInstData
├── exec_context.hh               ← Minor ExecContext for register/memory I/O
├── activity.hh / activity.cc     ← Activity recorder for CPU idling
├── stats.hh / stats.cc           ← Pipeline statistics
├── trace.hh                      ← Debug tracing helpers
├── BaseMinorCPU.py               ← Python parameter class
├── MinorCPU.py                   ← Python CPU configuration
└── SConscript                    ← Build definitions

Configuration Parameters

Code Example: Execute Stage Evaluate

// Simplified view of Execute::evaluate() from minor/execute.cc
void Execute::evaluate()
{
    // Try to commit completed instructions at head of pipeline
    for (int i = 0; i < commitLimit; ++i) {
        MinorDynInstPtr inst = getInput();
        if (!inst) break;

        // Check scoreboard for RAW hazards
        if (!scoreboard.canInstIssue(inst)) {
            // Stall: source operand not ready
            break;
        }

        // Find available functional unit
        FuncUnit *fu = findFuncUnit(inst->staticInst->opClass());
        if (!fu || fu->isBusy()) {
            // Structural hazard: no FU available
            break;
        }

        // Dispatch to functional unit
        fu->issue(inst);

        // For memory ops, send to LSQ
        if (inst->isMemRef()) {
            lsq.pushRequest(inst);
        }
    }

    // Process FU completions and mark registers ready
    for (auto &fu : funcUnits) {
        if (auto inst = fu->getCompletedInst()) {
            scoreboard.markRegReady(inst->destReg());
        }
    }
}

Minor vs O3 Comparison