arch — Instruction Set Architectures

Architecture Overview

gem5 supports multiple instruction set architectures through a plugin-style design. The arch/generic directory defines abstract base classes (InstDecoder, BaseMMU, BaseISA, BaseTLB), and each ISA directory provides concrete implementations. This allows the CPU models to remain ISA-agnostic while still accurately modeling architecture-specific behavior.

graph TB
    subgraph "Generic Base Classes"
      InstDecoder["InstDecoder\n(instruction fetch/decode)"]
      BaseMMU["BaseMMU\n(memory management)"]
      BaseISA["BaseISA\n(ISA state)"]
      BaseTLB["BaseTLB\n(TLB interface)"]
      PCStateBase["PCStateBase\n(program counter)"]
    end

    subgraph "x86"
      X86Dec["X86::Decoder"]
      X86MMU["X86::MMU"]
      X86ISA["X86::ISA"]
      X86TLB["X86::TLB"]
    end

    subgraph "ARM"
      ArmDec["ArmISA::Decoder"]
      ArmMMU["ArmISA::MMU"]
      ArmISAc["ArmISA::ISA"]
      ArmTLB["ArmISA::TLB"]
    end

    subgraph "RISC-V"
      RiscvDec["RiscvISA::Decoder"]
      RiscvMMU["RiscvISA::MMU"]
      RiscvISAc["RiscvISA::ISA"]
      RiscvTLB["RiscvISA::TLB"]
    end

    InstDecoder --> X86Dec
    InstDecoder --> ArmDec
    InstDecoder --> RiscvDec
    BaseMMU --> X86MMU
    BaseMMU --> ArmMMU
    BaseMMU --> RiscvMMU
    BaseISA --> X86ISA
    BaseISA --> ArmISAc
    BaseISA --> RiscvISAc
    BaseTLB --> X86TLB
    BaseTLB --> ArmTLB
    BaseTLB --> RiscvTLB
    

ISA Plugin Pattern

gem5's ISA abstraction uses a combination of C++ virtual interfaces and build-system-level selection. At compile time, one or more ISAs are enabled via the build configuration. The CPU model calls generic methods on InstDecoder, BaseISA, and BaseMMU, which dispatch to the ISA-specific implementation.

Generic Base Classes

// arch/generic/decoder.hh
class InstDecoder : public SimObject
{
  protected:
    void *machInst;  // ISA-specific machine instruction

  public:
    // Feed bytes from instruction fetch
    virtual void moreBytes(const PCStateBase &pc, Addr fetchPC) = 0;

    // Check if a complete instruction is available
    virtual bool instReady() const = 0;

    // Decode and return a StaticInst
    virtual StaticInstPtr decode(PCStateBase &nextPC) = 0;

    // Reset decoder state (e.g., on branch)
    virtual void reset() {}
};

// arch/generic/mmu.hh
class BaseMMU : public SimObject
{
  public:
    enum Mode { Read, Write, Execute };

    BaseTLB *dtb;  // Data TLB
    BaseTLB *itb;  // Instruction TLB

    // Address translation
    virtual Fault translateAtomic(const RequestPtr &req,
        ThreadContext *tc, Mode mode) = 0;

    virtual void translateTiming(const RequestPtr &req,
        ThreadContext *tc, Translation *translation,
        Mode mode) = 0;

    // TLB maintenance
    virtual void flushAll() = 0;
    virtual void demapPage(Addr vaddr, uint64_t asn) = 0;
};

PC State Abstraction

Each ISA has a different program counter representation. x86 needs microcode PC tracking, ARM needs Thumb/ARM mode bits, and RISC-V needs compressed instruction awareness. PCStateBase provides the polymorphic interface.

class PCStateBase
{
  protected:
    Addr _pc = 0;
    Addr _npc = 0;
    MicroPC _upc = 0;
    MicroPC _nupc = 0;

  public:
    Addr pc() const { return _pc; }
    Addr npc() const { return _npc; }
    MicroPC upc() const { return _upc; }

    virtual PCStateBase *clone() const = 0;
    virtual void advance() = 0;
    virtual bool branching() const = 0;
};

Supported ISAs

Instruction Decode Pipeline

sequenceDiagram
    participant CPU as CPU Frontend
    participant Dec as InstDecoder
    participant Cache as StaticInst Cache
    participant Exec as Execution Unit

    CPU->>Dec: moreBytes(pc, fetchPC)
    Dec->>Dec: Buffer and parse bytes
    CPU->>Dec: instReady()?
    Dec-->>CPU: true
    CPU->>Dec: decode(nextPC)
    Dec->>Cache: lookup machInst
    alt Cache hit
      Cache-->>Dec: Return cached StaticInst
    else Cache miss
      Dec->>Dec: Create new StaticInst
      Dec->>Cache: Insert into cache
    end
    Dec-->>CPU: StaticInstPtr
    CPU->>Exec: execute(StaticInst, ThreadContext)
    

Fault Hierarchy

Each ISA defines its own fault classes inheriting from FaultBase. Faults represent architectural exceptions (page faults, interrupts, traps) and carry ISA-specific information for handler dispatch.

// Generic fault base
class FaultBase : public RefCounted
{
  public:
    virtual const char *name() const = 0;
    virtual void invoke(ThreadContext *tc,
                        const StaticInstPtr &inst) = 0;
};

typedef RefCountingPtr<FaultBase> Fault;
const Fault NoFault = nullptr;

Key Components Reference

Sub-Modules

Cross-Module Connections

graph LR
    arch["arch\n(ISA decoders, faults, MMU)"]
    sim["sim\n(SimObject, EventQueue)"]
    cpu["cpu\n(O3, Minor, KVM)"]
    mem["mem\n(cache, DRAM)"]
    base["base\n(BitUnion, types)"]

    base -->|"BitUnion, Addr"| arch
    sim -->|"SimObject base"| arch
    arch -->|"StaticInst, Faults"| cpu
    arch -->|"MMU, TLB"| mem
    cpu -->|"ThreadContext"| arch
    

Glossary